CALL 1 SECURE ENCLAVE CHIPLETS_Amendment 2

CALL 1 SECURE ENCLAVE CHIPLETS This Broad Agency Announcement (BAA) Call solicitation is issued in accordance with the Revolutionary Federal Acquisition Regulation Overhaul (RFO) subpart 35.102. NAICS Code: 541713, Nanotechnology research and development laboratories or services, all fields of science Federal Agency Name and Contracting Officers: SAF/AQC, Ms. Natalie Sitkowski natalie.sitkowski@us.af.mil SAF/AQC, Ms. Dimitria Antonopoulos, dimitria.antonopoulos@us.af.mil SAF/AQC, Mr. Stephen Colvin stephen.colvin.2@us.af.mil Technical POC: SAF/AQ: Mr. Matthew Karijolic matthew.karijolic@us.af.mil Broad Agency Announcement Title: This is a combined synopsis/solicitation under the State-of-the-Art (SOTA) Microelectronics Adoption BAA. Call 1, titled Secure Enclave Chiplets Broad Agency Announcement Number: 26-S-1358, Call 001 (Secure Enclave Chiplets) Broad Agency Announcement Type: This is the initial announcement for Call 1. This will be a Two-Step Call solicitation. Step 1: WHITE PAPER DUE DATE AND TIME: White Papers will be accepted until 27 Jul 2026 at 5:00pm Eastern Time (ET). White Papers may be submitted at any time during this period. White Papers received after the specified date and time will be considered late in accordance with RFO 52.215-1(c)(3) and will not be reviewed. Questions pertaining to this Call may be submitted for the USG s consideration NLT 15 July 2026 at 5:00pm ET. Please email all questions to SE_PI@us.af.mil. Step 2: FULL PROPOSAL DUE DATE AND TIME: To be provided in the Requests for Proposal (RFP) sent to Offerors that submit White Papers considered to be of further interest to SAF/AQC. Full Proposals received after the specified date listed in a formalized Step 2 RFP and time will be considered late. Submission POC: White Papers must be submitted via email to SE_PI@us.af.mil. FULL TEXT CALL 1 (Secure Enclave Chiplets) SECURE ENCLAVE CHIPLETS OVERVIEW The Department of War (DOW) invites Offerors to submit Pilot Project chiplet designs with innovative and novel technical solutions which address all aspects of SOTA microelectronics and composable systems, focusing on the Secure Enclave Chiplets objectives below. This requires delivering enduring, secure, interoperable, and highly reusable chiplet architectures tailored for High-Demand Mission Areas (e.g., Radio Frequency/Electronic Warfare (RF/EW), munitions, security, and/or autonomy). Many DOW microelectronics projects operate in varying classification environments, including highly classified environments (collateral, Sensitive Compartmented Information, and Special Access Programs). The USG intends for much of the development to occur at the UNCLASSIFIED or Controlled Unclassified Information (CUI) level. Notice of intent to perform classified work as a result of this Call must be provided to the USG Contracting Officer. If the Offeror intends to perform any classified work, it must be done so at their facility (or a subcontractor/sub-awardee s facility). The Offeror will need to provide a Facility Accreditation Letter (FAL) for each facility to the Contracting Officer no later than (NLT) contract award. This BAA Call may result in the award of a Federal Acquisition Regulation (FAR)-based contract or an Other Transaction for Prototype Project pursuant to 10 U.S.C. 4022. The Government is not obligated to make any awards as a result of this Call, and all awards are explicitly subject to the availability of funds and successful negotiations. The USG will not reimburse any offeror for White Paper or Proposal costs associated with responding to this solicitation. The USG reserves the right to modify the solicitation requirements of this BAA Call at its sole discretion. SECURE ENCLAVE CHIPLETS STATEMENT OF OBJECTIVES (SOO) BACKGROUND Secure Enclave is a DOW acquisition program to provide the USG with a secure, trusted source of state-of-the-art (SOTA) microelectronics (ME) wafers and packaged parts. In partnership with Intel Corporation, Secure Enclave will ensure key aspects of end-to-end ME manufacturing are performed securely and onshore. This Call will solicit Pilot Projects to act as pipe cleaners that test the Secure Enclave design and manufacturing capabilities while fostering development of chiplets and interfaces needed to affordably insert SOTA ME into DOW programs. Beyond Secure Enclave, the DOW requires a fundamental shift in how it develops, procures, and sustains SOTA ME to combat cost growth, mitigate obsolescence, and accelerate the insertion of advanced technology into national security systems (NSS). Monolithic and bespoke silicon designs have become increasingly complex and prohibitively expensive. As a result, the DOW is transitioning toward composable chiplet architectures. The USG requires the development of SOTA chiplets utilizing open interconnects to foster a robust, affordable, interoperable chiplet ecosystem. This "chiplet-first" approach allows the DOW to apply Intel 18A SOTA silicon, where maximum performance is mission-critical, while integrating mature, trusted, non-SOTA, or Commercial-off-the-Shelf (COTS) silicon for standard functions. The USG aims to drastically lower Non-Recurring Engineering (NRE) and adoption costs, improve overall manufacturing yield, and aggregate demand across shared mission sets (such as RF/EW, munitions, security, autonomy, etc.). Ultimately, this Call seeks to demonstrate that a modular, open-standard chiplet ecosystem can deliver next-generation capability to the warfighter faster and more affordably than traditional approaches. The scope detailed below is a USG Statement of Objectives (SOO) the USG seeks to achieve during the performance for any awards made under this Call. The USG expects Offerors to propose a defined and detailed Contractor Statement of Work (CSOW) that includes ALL three (3) Objectives listed in Section 2.0 below. The USG reserves the right to make edits to the SOO prior to the release of a formal Step 2 Request for Proposals (RFP). SCOPE OBJECTIVE 1 Analyze The contractor shall analyze current and future DOW requirements within a single or multiple selected high demand mission area(s)/domain(s) and describe how their proposed SOTA chiplet advances DOW capability when integrated into a longer-term Multi-Chip Package (MCP) architecture. The contractor shall explicitly analyze anticipated demand for the proposed chiplet, if successful, and detail its applicability and performance benefits to DOW mission sets, including targeted Size, Weight, and Power (SWaP). The contractor shall calculate the projected unit demand across the USG and Defense Industrial Base (DIB) for the developed chiplet, if successful, and document any assumptions inherent in their demand estimates. The contractor is encouraged to partner with other DIBs and USG partners to derive their demand estimate. The contractor shall perform and deliver a gap analysis detailing intellectual property requirements absent from the current Intel 18A process node required to enable composable chiplet architectures and/or ecosystems. The contractor shall identify and deliver a listing of all missing functional Intellectual Property (IP) blocks, immature interconnects, and necessary military environmental qualifications required for long term success of the proposed chiplet and its surrounding architecture and/or ecosystem. The contractor shall document and justify the system-level partitioning of their proposed SOTA chiplet within a larger MCP architecture. This documentation must include: A clear description of which system functions are allocated to the newly designed SOTA chiplet (to be advanced using Intel 18A and Advanced Packaging via Secure Enclave). A description of which surrounding system functions are best allocated to external, non-SOTA or COTS companion chiplets within the broader MCP ecosystem. OBJECTIVE 2 Design & Deliver The contractor shall design a highly reusable, highly capable MCP architecture, inclusive of at least one newly designed SOTA chiplet ready for tape-out, that advances the DOW s use of SOTA ME. The contractor may propose a clean sheet design, iteration of a legacy design that adds SOTA capability via a chiplet, or a decomposition of an existing USG ME architecture that includes integration of Intel 18A silicon or use of Intel s onshore, Advanced Packaging. The contractor shall, to the maximum extent practical, leverage representative models including emulation, simulation, and digital twins to increase probability of achieving first-pass tape-out success. The contractor shall deliver fully functional software Transaction Level Models (TLMs) representing the proposed chiplet architecture prior to any physical tape-out. The contractor s design shall prioritize open standards, using Intel advanced packaging technologies (e.g., Embedded Multi-die Interconnect Bridge, etc.). The contractor shall, at the end of the Period of Performance, deliver a finalized chiplet design in a verified…